This invention relates generally to a metal oxide semiconductor field effect transistor (MOSFET) and more particularly to a V-groove metal oxide semiconductor field effect transistor (V-MOSFET).
MOSFETs of planar construction have been used as integrated circuit elements. That is, the device includes a body of semiconductor material of one conductivity type with spaced inset regions of opposite conductivity type forming source and drain regions with the junctions extending to the surface of the device and defining therebetween a channel region.
One problem with planar devices of the type described is that a large surface area is required for making surface contact to the source and drain regions. Another problem encountered with such circuits has been the control of spacing between the inset regions of opposite conductivity type to achieve small spacing therebetween, that is, short channels.
An improvement has been the V-MOSFET. In this transistor the channel length is controlled by the difference in depth of two insert regions of opposite conductivity type diffused into a body of semiconductor material of a conductivity type opposite to the conductivity type of the first inset region and of the same conductivity type of the second inset region. A V-groove is formed in the body and extends through the two junctions formed by the two insets. An insulating layer is deposited over the surface of the groove and carries the gate electrode. The channel length is controlled entirely by controlling diffusion of the inset regions. In the prior art planar source and drain contacts are made to the inset and body region. Where VMOS transistors are manufactured as part of integrated circuits the semiconductor body is designated as common source electrode and the inset regions of like conductivity as the body are designated individual drain electrodes. A fourth electrode is connected to the inset region of opposite conductivity type as the semiconductor body and is the back gate electrode. In integrated circuits the back gate electrode is used to provide substrate to source bias.
A different category of VMOS transistors is the VMOS power transistor. The structure of the VMOS power device is identical to the devices described above with the exception that the semiconductor body is the drain electrode and the insert is the source electrode. Power transistors do not require a separate bias between back gate and source. It is therefore customary in the present art to provide planar contacts which combine both the source and the back gate electrode. The contacts are thus comprised of exposed regions of opposite conductivity. It is known from literature and experience that the etching rates of oxides grown over regions of opposite conductivity differ. Differences in etch rates add complexity to processing. Any residual oxide left in the contact windows results in either a floating source contact or a floating back gate contact or an electrode with high contact resistance, rendering the device useless for high power applications.
A prior art power V-groove insulated gate field effect transistors is illustrated in FIG. 1. The insert regions, forming the source and the channel have their respective junctions terminating at the surface and at the groove walls. They are manufactured by two photomasking steps. A third masking step is required to delineate and etch the V-groove. A fourth masking step provides for contact windows to the source and channel back gate region. After metallization a fifth masking step delineates the metal electrodes. Final passivation of the device requires a sixth masking step to expose the bonding pads for wire bonding to the device package.